Nitin Saurabh is working on his Master's thesis, surveying results in the area of algebraic complexity.
Karteek Sreenivasaiah surveyed lower bound techniques for Boolean circuits for his master's thesis, which he completed in July 2010. He is currently working towards his doctoral degree, and is interested in problems concerning Boolean and arithmetic circuits.
Prajakta
Nimbhorkar worked on a variety of problems concerning
planar graphs and planar layouts. A high point of her research,
co-authored with many others, is a log-space algorithm for determining
whether two planar graphs are isomorphic. She is also interested in
circuits, randomness, and algebraic structures. She defended her
doctoral thesis, titled
Complexity Analysis of Some Problems
in Planar Graphs, Bounded Tree-width Graphs and Planar Point Sets,
in October 2010.
Currently, Prajakta is at the Chennai Mathematical Institute.
B. V. Raghavendra
Rao worked on problems concerning counting
classes, arithmetic circuits, algebraic complexity, and the complexity
of some isomorphism questions.
He defended his
doctoral thesis, titled
A study of width bounded arithmetic circuits, and the complexity
of matroid isomorphism, in March 2010.
Currently, Raghavendra is a post-doctoral fellow
at Saarland University, Germany.
Nutan Limaye
worked on parallel computation techniques centred around LogCFL
for her M.Sc. project, which she completed in June 2005.
Towards a PhD, Nutan worked on problems concerning circuits,
logarithmic space, and context-free languages. She defended her
doctoral thesis, titled
Exploring LogCFL using Language Theory, in December 2009.
Currently, Nutan is at the CSE dept at IIT Bombay.
Jayalal Sarma
worked on derandomization techniques
for his M.Sc. project, titled
Refining Randomness and Applications to Derandomization,
which he completed in July 2004.
Towards a Ph.D., he worked on problems concerning circuits,
algebraic structures/computations, and derandomization. He defended
his doctoral thesis, titled
Complexity Theoretic Aspects of Rank, Rigidity and Circuit
Evaluation, in February 2009.
Currently, Jayalal is in the CSE dept at IIT Madras.